Hello, we are hiring candidates in the following area, please feel free to distribute.

Contact: joonyoung.kim at intel dot com

Description

 Successful candidate will be responsible for scoping, developing, deploying and supporting design and validation tools for Intel’s next generation multi-core CPU projects. She/he will support Logic Design Engineers and Circuit Design Engineers who design and validate RTL code, custom circuit design blocks and cell-based design blocks. Successful candidate will devise innovative tools and methodologies to address a wide variety of complex, non-repetitive design problems in one of the following areas: 1) Logic design and simulation, source control management, testbench generation, formal verification, lint rule checkers and formal equivalence verification tools, 2) custom circuit design tools used for static timing analysis, reliability verification, noise analysis, parasitic extraction and electrical rule checking, 3) cell-based design tools and flows heavily dependent on industry standard synthesis, place and route tools. Successful candidate will develop project-specific wrappers around existing design tools and will also develop Perl, C/C++ or TCL tools from scratch. She/he will provide training to engineers located in multiple sites and will support team members as tool and methodology issues arise. 

Qualifications

Minimum Requirements:

You must possess a Bachelor of Science degree in Electrical Engineering or Computer Engineering with 1-3 years of experience or coursework in the following:

– Experience writing code and scripts using Perl, C, C++ or TCL

– Strong problem-solving skills

– Customer service skills including solid verbal and written communication a must since design team is spread across multiple sites

Preferred Qualifications:

– Masters degree in EE or CE with coursework in VLSI area

– Experience with front-end design tools, verification techniques and methodologies including, System Verilog, lint rule checking, formal verification and test bench creation

– Experience with design automation tools with focus on circuit design, experience with timing analysis/verification, noise analysis, reliability verification and debugging 

– Good understanding of semiconductor physics and layout design

– Experience with back-end design tools and methodologies with focus on CBD and APR; including experience with APR tools – floorplanning, placement, routing and clocking flows and RTL synthesis, scan insertion and power reduction techniques

– Computer architecture and micro-architecture knowledge

– Familiarity with networked computing environment and impact on simulation runtimes