Home Job Postings 반도체 공정개발 분야(Logic TD & etc) 전문 engineer 채용(multiple position) This topic has replies, 1 voice, and was last updated 8 years ago by younpartners. Now Editing “반도체 공정개발 분야(Logic TD & etc) 전문 engineer 채용(multiple position)” Name * Password * Email Topic Title (Maximum Length 80) Company * Location Expires at ▣Company: Top Semiconductor Company ▣Location: Hwasung or other location in Korea ▣Job Requirements -Logic TD [7mm] 업무경험 – CMOS Device Design – Advance CMOS Devices (FD SOI, UTB FET, FinFET, Nanowire, etc) – Strain engineering & Mobility boosting (SMT, SiGe, etc) – FEOL Reliability – Device, Circuit interface 전문지식 – CMOS Device Physics – CMOS Process and Integration – Contact Resistance – Tr Reliability 필수 Check Point – Impact of Baisc Parameter on Planar & Advanced Device Performance – Basic CMOS Integration & its impact on Reliability – Impact of Device Performance & Variability on Circuit Performance – Impact of Contact Resistance on Advanced Device Performance [10nm] 업무경험 – Logic Device Unit Process Experience – Logic Device Process Integration(FEOL/MEOL/BEOL) – Logic Device Electrical Characteristics Analysis – Semiconductor Product Yield Improvement/management – Semiconductor Manufacturing Experience 전문지식 – Expert understanding of Logic Process Flow – Expert understanding of Semiconductor manufacturing system – Solid understanding of Device Physics(CMOS FinFet transistor) – Good understanding of Semiconductor Unit Processes – HKMG and SiGe epi experience are preferred 필수 Check Point – Good Communication Skills (verbal and written) – Leadership and team management ability – Good work relationship with other co-workers or teams – Passion to be world best logic company – Strong Organization Skills – Proven problem solving ability [BEOL] 업무경험 – BEOL integration – BEOL process assumption development – Definition of BEOL GRs – Dry etch/lithography – Macro design and verification 전문지식 – Lithrgraphy/OPC – BEOL process integration – Graphene/carbon nanotube – BEOL reliability (EM/TDDB, CPI) – Patterning technology 필수 Check Point – Communication skill (KOREAN and English) – Experience of macro design – Understanding Process assumption and GRs [Design rule] 업무경험 – Design rule development – Standard library layout design – SRAM bit-cell development – Device/integration experience – PDK (DRC) experience – Photo/OPC experience 전문지식 – Expert understanding of Logic Process Flow – Expert understanding of Semiconductor manufacturing system – Solid understanding of Device Physics(CMOS FinFet transistor) – Good understanding of Semiconductor Unit Processes – HKMG and SiGe epi experience are preferred 필수 Check Point – Good Communication Skills (verbal and written) – Leadership and team management ability – Good work relationship with other co-workers or teams – Passion to be world best logic company – Strong Organization Skills – Proven problem solving ability [Device] 업무경험 – CMOS Device Design – Advanced CMOS Devices (FD SOI, UTB FET, FinFET, Nanowire, etc) – FEOL Reliability – Device – Circuit interface 전문지식 – CMOS Device Physics – CMOS Process and Integration – Contact Resistance – Tr Reliability 필수 Check Point – Impact of Basic Parameter on Planar & Advanced Device Performance – Basic CMOS Integration & its impact on Reliability – Impact of Device Performance & Variability on Circuit Performance – Impact of Contact Resistance on Advanced Device Performance 공정개발 [Cleaning] 업무경험 – 반도체 미세공정 제품 Cleaning Tool & Chemical Solution 개발 – 3D Fin 향 Dry Cleaning 공정 개발 – Gate Last 공정향 RPG/RMG Wet 공정 개발 – Metal Wet Etch 공정 개발 및 Low-k 세정 기술 개발 – 차세대 Device 향 P/C 제거 기술 개발 – Chemical (etchant, surfactant) 업체 경력자 및 전공자 – CLN 설비, 소재 개발 유경험자 전문지식 – Inorganic / Organic Chemistry / Electrochemistry – Surface Science and Surface Chemistry – Physical Chemistry – Fluid Mechanics, Hydrodynamics 필수 Check Point – 반도체 Wet 공정 개발 경험 – 반도체용 Chemical 개발 경험 – 반도체 공정 경험 (3년 이상 선호) [CMP] 업무경험 – CMP Tool & 공정 개발 – Chemical (etchant, surfactant, slurry) 업체 경력자 및 전공자 – CLN/CMP 설비, Slurry, Pad, Disk 개발 유경험자 – 유체역학 및 설비, leaning 관련 Simulation 가능자 – 반도체 Integration 경험자 (제품 이해도) – Simulation 가능자, 설비 설계/제어/자동화 분야 근무 전문지식 – CMP Process & Gate Last Process – CMP Slurry Chemistry & Role of Additive – Cu/Low-k Damascene CMP, Post CMP Cleaning – 반도체 CMP 기술 및 원리 구동 원리 이해 및 설계 가능 능력 필수 Check Point – CMP 공정 지식 (CMP공정 Mechanism, Tool 활용 능력) – Slurry/Pad 개발 경험 – 반도체 공정 경험 (3년 이상 선호) [ETCH] 업무경험 – DRAM/ FLASH/ Logic 제품 개발 – 각 제품별 단위 Module Dry etch 공정 개발 – Dielectric / Conductor Etch 공정 개발 – 차세대 Device 향 Dry etch 공정 개발 – 각 종 Etcher 설비 개발 전문지식 – DRAM/ FLASH/ Logic 제품에 대한 이해 – 각 제품별 Dry etch 공정의 이해 – Dry Etch 설비 이해 및 활용 – Dry etch 기본을 이루는 플라즈마에 대한 이해 필수 Check Point – Etch 공정에 대한 기본 개념 – Dry etch 설비 [OPC] 업무경험 – Photolithography patterning simulation – Optical proximity correction and verification – Design for manufacturing – Mask data preparation – Design rule extraction – Optical system design 전문지식 – Knowledge of Optics and Lithography – Knowledge of Photolithography simulation and OPC – Working experience on Unix/Linux – Programming language (C/C++, Tcl, Python) 필수 Check Point – Photolithography simulation technique – Skill of using OPC software – Layout design rule experience – OPC technology trend [Photo] 업무경험 – Lithography (공정, Simulation, OPC, RET) – Mechatronics, 제어 / Laser, 광공학, 계측 – Programming(Coding) 및 Simulation – Vacuum(Vacuum 설비 Defectivity 제어), Plasma 등 – 포토 설비 응용 기술 (Scanner/Track/Overlay 측정) – Device integration 관련 포토 공정 응용 – Defect engineering 전문지식 – Programming & Simulation(RCWA, FDTD, FEM등) – 포토 관련 설비 이해 (Scanner/Track/Overlay) – Device 구조, 작동원리 이해 – Layout handling, OPC sequence, Mask 제작 공정 이해 – 포토 관련 defect 발생 mechanism 이해 필수 Check Point – Matlab or Labview Programming 경험 – Photo 공정 line-work 경험 – Data에 기초한 합리적인 분석능력 – PHOTO 설비 운영 및 개발 경험 [DNI] 업무경험 – ALD, CVD 용 Precursor 합성 및 증착기술 개발 – device integration 및 특성 분석 – 구조체 열유동 및 기계 강성 시뮬레이션 – Low-k ALD 박막 공정 개발 전문지식 – Diffusion, ALD/CVD 공정/설비 – Implantation, 열처리 공정/설비 – 박막의 이해, 물성분석기 ((XPS, XRD, AES, TEM) – Flash memory device integration 및 신뢰성 – 무기화학 또는 유기금속화학 – 박막재료공학, 전기전자공학, 기계 공학 – 고체물리/응집물리/플라즈마/레이져전공 필수 Check Point – Diffusion, ALD/CVD 공정/설비 경험 – Implantation/열처리 공정에 대한 이해 – Plasma 원리 및 모니터링 방법 – OPC technology trend [Thin film] 업무경험 – Metallization 공정 기술 – ALD process and deposition 공정 기술 – Plasma 활용 film 증착 기술 – film 분석기술 및 electrical 분석 기술 – High vacuum chamber 내 gas flow 이해 전문지식 – PVD 설비 및 공정개발 – PE-CVD 설비 및 공정개발 – Ternary material 공정 이해 – ALD-process 공정 이해 필수 Check Point – Depositon 공정 기술 ( PVD or CVD or ALD) – Metal 공정기술 및 설비기술 (Gas, Plasma, high vacuum chamber 등) – Thinfilm 분석 기술(기기분석 기술 및 해석) ▣ 채용조건 – Compensation & Benefit: 경력에 따른 개별 협의 ▣ 전형방법 – 서류 및 면접 전형 – 서류 전형에 합격한 분에 한하여 개별 연락을 드립니다. ▣ 제출서류 – 국/영문 이력서 (MS word 형식) ▣ 연락처 Email : experiencedhire@consultant.com or dave@younpartners.com I agree to the terms of service Update List
