저희 회사에서 아래에 관련된 engineer를 구합니다.
반도체쪽의 defect에 관련된 경험이 있으시거나 현재 관련된 일을 하시는 분의 지원을 바랍니다.
저희 회사는 미네소타에 있습니다. 미네소타가 추움의 대명사로 아시는 분들이 많으신데…전혀 그렇지 않습니다. 와보시면 압니다…
제 이름을 클릭하시면 저에게 이메일을 보내실수 있으십니다.

Candidates will be part of an Advanced Devices group that is responsible for Defect reduction and yield improvement working on complex non-volatile memory circuits and discrete non-volatile devices.

The candidate’s responsibilities include:

Responsible for developing in-line defect jobs and automated defect review Identifying process layer and unit process steps that are generating defects implementation of in-line defect metrology steps to continuously monitor pilot line

Responsible of the selection of defect related tools
Work on implementing an in-line to end of line yield correlation
Generation of pareto defect charts for critical layers with associated action items

Work within a team to drive defect down to a set goal
The candidate must have strong, cross-functional understanding of unit process and process integration

The candidate must be able to lead cross-functional teams that harbors innovation and achieves goals
Coordinate activities with integration, yield, FA and other engineering groups.

Qualifications
This position is only for experienced candidates looking for a challenge.

Candidate must have a MS/PHD in Electrical Engineering degree (or equivalent). Must have DEFECT experience in semiconductors (minimum of 5 years). Experience in working on defect reduction in an R&D or production environment. Must have strong verbal and written communications skills.

We know we are looking for a unique individual. And we know our standards are high. But the rewards are great.

Working on state-of-the-art projects will keep you excited about your work. Working in a team environment, you will be exposed to different engineers and will have the opportunity to share your knowledge and learn from them. Seagate believes this is critical to the growth of our employees as well as our Company. This is an exciting opportunity.