– Title: Sr ASIC Design/Verification Engineer
– Company: Integrated Device Technology, Inc (www.idt.com)
– Location: San Jose, CA
– Contact: jechan.kim@idt.com

*** Responsibilities
– Create verification plan at module and chip level for complex IC.
– Develop test bench at module and chip level using Verilog or System Verilog.
– Develop efficient system/chip level test and regression environment and scripts.
– Develop behavioral models and BFM.
– Generate test case and run simulation to achieve code coverage and function coverage.

*** Requirements
– MSEE with 3-7 years in design and verification proficiency
– Solid knowledge of scripting language like TCL, perl and C++.
– Knowledge of verilog PLI/Direct C and systems C is helpful.